1. Field of the Invention
This invention relates to a semiconductor nonvolatile memory device such as an EEPROM (Electrically Erasable Programmable Read Only Memory) device or a flash memory device, and a memory inspection method for inspecting a nonvolatile memory device.
2. Description of the Prior Art
Computer systems such as microcomputers are used for various applications at present, and semiconductor nonvolatile memory devices such as an EEPROM and a flash memory are used frequently as information storage media for the computer systems. A nonvolatile memory allows temporary storage of digital data and updating of the stored digital data and can maintain the stored data even when no electric power is supplied.
An example of a nonvolatile memory will be described below with reference to FIGS. 1 and 2. FIG. 1 shows a general structure of an EEPROM which is a kind of nonvolatile memory, and FIG. 2 shows a memory cell array of the EEPROM.
EEPROM 100 as an example of a nonvolatile memory includes a multiplicity of memory cells 101 arranged in a two-dimensional structure wherein memory cells 101 are connected in a matrix in X and Y directions as a whole as shown in FIG. 2. A plurality of X selector transistors 102 and a plurality of Y selector transistors 103 are connected in a matrix to the multiplicity of memory cells 101. X/Y selector transistors 102, 103 are provided to select memory cells 101 one by one.
Each memory cell 101 stores and holds respective binary data and assumes a first state in response to write data "1" which is one of the binary data, but assumes a second state in response to erase data "0" which is the other of the binary data. Passing current through memory cell 101 is relatively high write current when memory cell 101 is in the first state, but is relatively low erase current when memory cell 101 is in the second state. The difference between the first and second states is provided, for example, by a difference in threshold voltage of the memory cell which corresponds to the amount of charge injected into the floating gate of the memory cell. The charge injected in the floating gate does not change in an ordinary condition, and this allows memory cells 101 to function as a nonvolatile memory.
EEPROM 100 includes a writing and erasing circuit (not shown) which controls memory cell 101 into the write state (first state) in response to an input of write data "1", but controls memory cell 101 into the erase state (second state) in response to an input of erase data "0".
EEPROM 100 further includes sense amplifier 104, to which memory cells 101 are connected through respective Y selector transistors 103. Also reference circuit 105 for generating a reference voltage is connected to sense amplifier 104. Reference circuit 105 includes a plurality of transistors, and sense amplifier 104 includes a plurality of transistors similarly.
Reference circuit 105 includes first transistor 111 to the gate electrode of which external bias power supply 120 is connected. Second transistor 112 is connected in series to first transistor 111. Second transistor 112 cooperates with third transistor 113 to form first current mirror circuit 121, and fourth transistor 114 is connected in series to transistor 113 of first current mirror circuit 121.
Second current mirror circuit 122 is formed from fourth transistor 114 of reference circuit 105 and first transistor 115 of sense amplifier 104. Second transistor 116 of sense amplifier 104 is connected in series to transistor 115 of second current mirror circuit 122.
Third current mirror circuit 123 is formed, in sense amplifier 104, from second transistor 116 and third transistor 117, and transistor 117 of third current mirror circuit 123 is connected to memory cells 101 through respective Y selector transistors 103 connected in parallel to each other.
Bias power supply 120 supplies a gate voltage to first transistor 111 of reference circuit 105, and a fixed drain current flows through first transistor 111. Since first to third current mirror circuits 121 to 123 are successively connected to this first transistor 111, reference circuit 105 after all supplies reference current corresponding to the drain. current of first transistor 111 to sense amplifier 104.
Reference circuit 105 generates the reference current as described above. The reference current is higher than erase current which is pass current of memory cell 101 in an erase state, but is lower than write current which is pass current of memory cell 101 in a write state. Sense amplifier 104 compares pass current of memory cell 101 with the reference current of reference circuit 105 and reproduces the binary data stored in memory cell 101 based on a result of the comparison.
EEPROM 100 having the structure described above can execute three operations of data writing, data erasure and data reproduction arbitrarily. In execution of data writing into EEPROM 100, the writing and erasing circuit selectively controls one of the multiplicity of memory cells 101 to a write state in accordance with input data to record write data "1", which is one of the binary data, into selected memory cell 101.
In reproduction of the thus written data, reference circuit 105 generates the reference current, which is higher than the erase current but lower than write current, and sense amplifier 104 compares the pass current of memory cell 101 with the reference current thereby to reproduce binary data "0", "1".
In order to erase the written, data described above, the writing and erasing circuit selectively changes the state of memory cell 101 from the write state to the erase state in accordance with input data to initialize the written data "1" of memory cells 101 to the erase data "0".
While EEPROM 100 can execute the three operations of data writing, data erasure and data reproduction as described above, in order to control memory cell 101 to the write state or the erase state, a predetermined time is required as seen from FIG. 3. FIG. 3 is a characteristic diagram illustrating the on-currents upon reading of a memory cell of an EEPROM in a non-used state with respect to the write time and the erase time. The write time signifies a duration of a high voltage pulse applied to a memory cell in order to control the memory cell to the write state, and the erase time signifies a duration of a high voltage pulse applied to a memory cell in order to control the memory cell to the erase state. As apparently seen from FIG. 3, in order to obtain prescribed on-currents for the write state and the erase state when data is to be read out from a memory cell, a write time and an erase time longer than a certain time length are required. However, the write time and the erase time required to obtain the prescribed respective on-currents for the write state and the erase state are not constant, but increase as the accumulated number of times by which data writing and erasing operations into and from the EEPROM are performed increases. FIG. 4 is a characteristic diagram illustrating on-currents upon reading of a memory cell of the EEPROM, whose characteristic has been deteriorated as a result of an endurance test performed for the EEPROM, with respect to the write and erase times. The endurance test signifies a test of rewriting data into a memory cell in order to decide whether the EEPROM is a good product or not. FIG. 5 illustrates on-currents upon writing/erasure of a memory cell with respect to the number of times of data writing operations in the endurance test.
It is a normal practice to set the write time and the erase time for EEPROM 100 on the assumption that the times required for data writing and data erasure are invariable. Therefore, if the accumulated number of times of data writing operations and data erasing operations increases and memory cells 101 are deteriorated accordingly, then the write current upon data reading from the memory cell decreases and the erase current increases as seen from FIG. 5. Progress of the decrease of the write current or the increase of the erase current makes it difficult to reproduce binary data by comparison with the reference current, and EEPROM 100 is disabled finally.
Therefore, before shipment after EEPROM 100 is fabricated, the endurance test described above is executed to detect failed memory cell 101. In the endurance test, the write data "1" is first recorded into and then reproduced from memory cell 101, and if the reproduced data is not "1", then memory cell 101 is decided to be a failed memory cell. Further, the erase data "0" is first recorded into and then reproduced from memory cell 101, and if the reproduced data is not "0", then memory cell 101 is decided to be a failed memory cell. Before shipment of EEPROM 100, such a sequence of operations as described above is repeated by a predetermined number of times for all of memory cells 101 of EEPROM 100, and when the number of memory cells 101 decided to be failed memory cells with respect to all memory cells of EEPROM 100 is greater than a tolerance, this EEPROM 100 is abandoned. If the number of failed memory cells 101 remains within the tolerance, EEPROM 100 is set so as to disable use of all of failed memory cells 101, and then this EEPROM 100 is shipped. Since the endurance test described above is executed for EEPROM 100, EEPROM 100 can be shipped as a product which is free from an initial failure.
EEPROM 100 at present, however, includes a very large number of memory cells 101, and a certain time is required for data writing or data erasure into or from memory cell 101 as described above. Therefore, an endurance test in which data writing, data erasure and data reproduction for memory cells 101 are repeated by a predetermined number of times requires much time, and this deteriorates the productivity in fabrication of EEPROM 100.
A nonvolatile memory device which can solve the subject of the conventional nonvolatile memory described above is disclosed in Japanese Patent Laid-Open No. 300499/89 (JP, 01300499, A. In the improved nonvolatile memory, external reference current is supplied to a sense amplifier to allow reproduction of write data with reference current of a level higher than a normal level or allow reproduction of erase data with reference current of another level lower than the normal level. When such an endurance test is executed for the nonvolatile memory, a memory cell can be tested with a reduced margin of current. Consequently, a failed memory cell can be detected rapidly and the endurance test can be completed in a reduced time. However, in order to use the method described above to execute an endurance test, it is required to produce the reference current having a higher or lower level and externally supply it to the nonvolatile memory, and an apparatus for exclusive use for generating and supplying the variable current must be prepared separately from the nonvolatile memory.
Japanese Patent Laid-Open No. 22860/91 (JP, 03022860, A) discloses another nonvolatile memory device which includes a built-in high voltage generation circuit which generates a high voltage to be used for a test of the nonvolatile memory. The high voltage generation circuit can generate and supply three or more different high voltages.